This invention relates generally to semiconductor processing methods and structures for determining alignment during semiconductor wafer fabrication.
Fabricating integrated circuitry devices on a semiconductor wafer typically involves a number of processing steps in which successive layers are formed and patterned atop one another. Typically, patterning occurs through the use of photolithographic masks which transfer patterns onto a semiconductor wafer. The masking step defines selected areas to be exposed on the wafer for subsequent processes such as oxidation, metal deposition, and impurity introduction.
Typically, a plurality of metallization layers are formed over the wafer in order to electrically interconnect the integrated circuitry devices formed thereon. As device dimensions and feature sizes continue to shrink, it becomes even more important that the photolithographic masks which are used to define substrate features are precisely aligned with the wafer during the masking step to minimize the risk of a misalignment between layers.
Many alignment schemes require the use of alignment targets that are defined on a semiconductor wafer in a previously-formed layer. Typically, an alignment target comprises a topographical mark which can be formed by etching into the wafer a plurality of steps with a defined height and width and a defined spacing between other similarly etched targets. The targets can be used to diffract a laser alignment beam generated by a photolithography machine, commonly known as a wafer stepper, during the masking process. The diffraction pattern is received by the wafer stepper and the relative position of the wafer and photolithographic mask is adjusted accordingly so that the patterns from the mask are transferred to the wafer in the precise location desired.
Other alignment schemes include regimes in which an operator visually inspects, through a microscope, the alignment between alignment targets. For additional discussion on alignment technologies, and in particular, the use of so-called vernier pattern technology, the reader is referred to U.S. Pat. Nos. 5,614,446, 4,742,233, 5,637,186, 5,017,514, 5,271,798 and 4,610,940.
As mentioned above, during the fabrication of integrated circuit structures, a number of metallization layers are formed. The metallization layers are typically separated from one another by an insulation layer. In order to minimize misalignment between the layers, it is important that the topography of the alignment targets be replicated from one layer to the next, since the locations of the resulting patterns on each layer are formed based on the precise registration between the photolithographic mask and the alignment targets on the previous layer.
To provide an overlying metallization layer without discontinuities or other flaws, it is desirable to provide an underlying substantially planar surface for the metallization layer. It has, therefore, become the practice to smooth the surface of a layer in preparation for a subsequently applied metallization layer by a process of planarization.
Conventional planarization techniques, such as plasma etching or reactive ion etching can be used to provide a smooth surface and a local planarization of the wafer. Such techniques can be used to preserve alignment targets which are etched into the layer because often times, the topography of such targets is much greater than the amount of material removed by the planarization. Yet, other planarization techniques which are more desirable in some instances can obliterate any alignment targets such that its use is difficult, if not impossible. One such planarization technique is known as chemical-mechanical polishing or CMP. Typically, CMP planarization of a wafer involves holding the wafer against a rotating polishing pad wet with a silica-based alkaline slurry and at the same applying pressure. Unlike the conventional planarization techniques, the CMP planarization technique provides a global planarization, that is, one that provides a large planarization range that generally covers the whole wafer surface. Since the planarization range is large, the alignment targets on a newly formed layer on the wafer will tend to lose decipherable topology after CMP processing. Accordingly, such alignment targets will fail to replicate the new alignment targets on the previous layer. This is acceptable as long as the planarized newly formed layer is transparent, such as in the case of an oxide, since a laser alignment beam from a wafer stepper, or a visual inspection will still be able to ascertain alignment. However, when the planarized newly formed layer is a highly reflective or opaque layer, as in the case of a metal, the alignment targets will typically not be suitably visible to the wafer stepper or visual inspector.
Accordingly, this invention arose out of concerns associated with providing improved methods and structures for determining semiconductor wafer alignment during wafer processing.
Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.